Metal-Oxide-Semiconductor (MOS) electrically programmable read-only memories (EEPROMS) frequently use memory cells that have electrically isolated gates (floating gates). These floating gates are typically completely surrounded by insulation and formed from a polychrystalline silicon (polysilicon) layer. Information is stored in the memory cells or devices in the form of the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunneling, etc., depending upon the construction of the cells. The cells are erased generally by exposing the array to ultraviolet radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 2,755,721; and 4,099,196. In some cases these cells are electrically erasable (EEPROM cells). An example of such a cell is shown in U.S. Pat. No. 4,203,158.
The invention of the present application is used with an EEPROM cell, particularly one which is electrically erasable, commonly referred to as a "flash" EPROM cell.
Due to the nature and design of flash EEPROM cells, the entire array must be erased in order to erase any one cell in that array. Generally, this has not been a problem in that each row (word line) is separately addressable and each column (bit line) is separately addressable or can be addressed in groups of 8 (comprising 1 byte) and that a large array can be formed from several small arrays, each of which can be erased individually. Further, prior to erasing the entire array, each memory cell in that array must be preconditioned.
Preconditioning is the process whereby a memory cell is programmed prior to erasure to avoid over-erasing the cell which can cause leakage within that cell resulting in false data readings. This occurs when a cell in the zero state undergoes an erase operation whereby it can be driven into the depletion mode. The column sense amplifier can read this current falsely as an erased cell. Therefore, proper preconditioning is necessary to avoid over erasing a single cell which can in turn cause an entire array to be defective.
When a row (word line) is found to be defective by a manufacturer (e.g., shorted to another row), it is desirable to be able to assign an alternate row to take its place. Using an alternate row can thus increase the yield of working memory chips. Due to the need to precondition each memory cell in the array, however, it is necessary to precondition each row in the array; those rows that are working as well as those rows determined to be defective in the manufacturing test stage.
An example of a method and apparatus for providing row redundancy in non-volatile semiconductor memories is shown in U.S. Pat. No. 5,233,559. The method and apparatus provides for preconditioning of each row of memory cells prior to erasing the memory array, including any rows containing defective cells as well as any redundant rows. Another example is shown in U.S. Pat. No. 5,327,383.
Similarly, post conditioning, a method for repairing over erased cells of a non-volatile memory array, must also be able to access shorted rows. An example of the use of post conditioning to repair over erased cells is shown in U.S. Pat. No. 5,237,5535.
A decoder is used to access rows. During preconditioning and post conditioning, this decoder is required to enable two adjacent rows: the row selected and the next row. The previous decoder design implements dual row selection by using device power supply, VCC, voltage level logic (see FIG. 4). This circuit is too slow to accommodate the read access rate desired for new, faster, flash memories.